Verilog
The physical data of variables in are divided into linear and register types. When defining these two types of variables, the bit width should be set, and the default value is 1 bit. Each bit of a variable can be 0, 1, x, z, where x represents a variable with no preset initial state, or a conflicting linear variable caused by two or more driving devices trying to set it to different values. Z stands for high impedance state or floating quantity.
Linear data, including lines, bars, words, etc. When driven by multiple excitation sources, different linear data have their own analytical methods to determine their final values.
The difference between them is that memory data keeps the last assignment, while linear data needs to be driven continuously.
The input port can be driven by net/reg, but the input port can only be net; The output port can be net/reg type, and the output port can only drive net; If the output port is allocated in the process block, it is of reg type, and if it is allocated outside the process block, it is of net type.
Declare a bidirectional port with the keyword inout. Inout ports cannot be declared as register types, but only as network types.
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Wire stands for straight-through, that is, as long as the input changes, the output immediately reflects unconditionally; Reg means that the output must have a trigger to reflect the input.
If not specified, it defaults to 1 conductor type. Specify the line type, which can be multi-bit or make the program readable. Wires can only be allocated continuously, while reg can only be allocated initially and always. Wire is used for continuous assignment statements, and reg is used for procedure assignment statements.
In a continuous assignment statement, the calculation result on the right side of the expression can immediately update the expression on the left. In understanding, it is equivalent to connecting a line directly after a logic, corresponding to the right side of the expression, and this line corresponds to the conductor. In the procedure assignment statement, the calculation result on the right side of the expression is put into a variable triggered by a certain condition, which can be declared as reg type. According to different trigger conditions, the process assignment statement can model different hardware structures: if this condition is the rising edge or falling edge of the clock, then this hardware model is a trigger; If this condition is the high or low level of the signal, then this hardware model is a latch; If this condition is the change of any operand on the right side of the assignment statement, then this hardware model is combinatorial logic.
The input port can be driven by wire/reg, but the input port can only be wire; The output port can be wire/reg type, and the output port can only drive wire; If the output port is allocated in the process block, it is of reg type, and if it is allocated outside the process block, it is of net type. Declare a bidirectional port with the keyword inout,
Inout port cannot be declared as reg type, only as wire type. Input and bidirectional ports cannot be declared as register types.
Simply put, the hardware description language has two purposes: 1, simulation, 2, synthesis.
Wire and reg should also be considered from these two perspectives.
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From the simulation point of view, HDL language is compiler-oriented (such as Modelsim), which is equivalent to software thinking.
At this point:
Connecting lines correspond to continuous assignment, such as assignment.
Reg corresponds to process assignment, such as always, initial.
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From the point of view of synthesizer, HDL language faces synthesizer (such as DC, etc. ), this should be considered from the circuit point of view.
At this point:
Variables of types 1 and wire are generally a line;
2.reg variable has two situations in always block:
The sensitive table after (1) is always in the form of (a or b or c), that is, it is still combinational logic when it is synthesized without clock edges.
The sensitive table of (after) is always in the form of (posedgclk), that is, with edges, usually sequential logic, which will include flip-flops.
In design, generally speaking, you don't know whether the previous stage is a register output or a combinational logic output, so it is a wire for this stage, that is, the wire type. It is up to you to decide whether the output signal is register output or combinational logic output, wire type or reg type. But in general, the external output of the whole design (that is, the output of the top module) needs register output, which is stable and has good fan-out ability.