With the development of technology, the integration of semiconductor chips is getting higher and higher, and the designed system is becoming more and more complex and larger, with higher performance requirements and higher power consumption, which brings new challenges to chip design engineers and EDA manufacturers. The design method of the chip has also changed, from the early stage of manual design, computer-aided design, computer-aided engineering and electronic automation design to the stage of system chip.
1, design definition and synthesis RTL code. The design definition describes the overall structure, specification parameters, module division, used interfaces, etc. Then the designer designs the modules according to the functional modules divided by the hardware design or reuses the existing IP cores. Usually, the hardware description language is used to describe the behavior of the circuit at the register transfer level, and Verilog/VHDL is used to describe the connection between logic units and the connection between input/output ports and logic units. The gate-level netlist describes the circuit with logical units, forms the circuit with instantiation and defines the hierarchical structure of the circuit. Pre-simulation, also known as RTL level simulation or functional simulation. Whether the logic function of the circuit is effective is verified by HDL simulator. In pre-simulation, it is usually irrelevant to the specific circuit implementation, and there is no timing information.
2. Logical synthesis. Establish a design and synthesis environment, input RTL source code into a synthesis tool, such as a design compiler, add constraints to the design, and then logically synthesize the design to obtain a gate-level netlist that meets the design requirements. The gate netlist can be stored in ddc format. The logic synthesis of circuits generally consists of three steps: transformation, logic optimization and mapping. Firstly, the RTL source code is converted into a general Boolean equation (GTECH format). The process of logic optimization attempts to complete the combination of library cells, so that the combined circuit can best meet the requirements of design function, timing and area; Finally, the logic units of the target process library are mapped into a gate-level netlist, which requires the process technology library of the semiconductor manufacturer to get the delay of each logic unit when mapping the circuit diagram. The results after synthesis include the timing and area of the circuit.
3. Layout planning. After getting the gate-level netlist, input the results into JupiterXT for layout planning. Layout planning includes macro-cell layout, power network synthesis and analysis, communication analysis, layout optimization and time sequence analysis.
4. Unit layout and optimization. Cell layout and optimization mainly define the placement position of each standard cell and optimize it according to the placement position. EDA tools widely support physical synthesis, unify layout and optimization with logical synthesis, introduce real connection information, and reduce the number of iterations required for time series convergence. Input the designed layout and gate-level netlist into a physical synthesis tool, such as a physical compiler, for physical synthesis and optimization. In PC, the design can be optimized in terms of timing, power consumption, area and routability to achieve the best result quality.
5. Static timing analysis (STA), formal verification (FV) and testability circuit insertion (DFT).
Static time series analysis is a detailed analysis method. By analyzing the delay information of all paths in the extraction circuit, the delay of the signal on the time sequence path is calculated, and the errors that violate the time sequence constraints such as whether the setup time and the hold time meet the requirements are found out. Static timing analysis should be carried out after the completion of logic synthesis, layout optimization, wiring completion and other steps in the back-end design.
Formal verification is an equivalence check in logic function, which judges whether the two designs are equal in logic function according to the circuit structure, and is used to compare the functional consistency between RTL codes, between gate-level netlist and RTL codes, and before and after the modification of gate-level netlist.
Design for testability. The logic circuit generally adopts the testability structure of scanning anchor chain, and the input/output port of the chip adopts the testability structure of boundary scanning to increase the controllability and observability of the internal nodes of the circuit. Generally, the insertion and optimization of swept frequency anchor circuits are carried out after logical synthesis or physical synthesis.
6. Post layout optimization, clock tree synthesis and wiring design. On the basis of physical synthesis, Astro tools can be used to further optimize the later layout. On the basis of optimizing the layout, the clock tree is comprehensively wired. At every stage of design, Astro will consider timing, signal, power integrity, area optimization and wiring congestion. It can integrate physical optimization, parameter extraction and analysis into every stage of layout and wiring, and solve the complicated problems related to the ultra-deep submicron effect in design.
7. Extraction of parasitic parameters. Extract parasitic resistance and capacitance values generated by internal interconnection on the layout. This information is usually converted into a standard delay format and marked back to the design for static timing analysis and post-simulation. Using the designed layout, parasitic parameters are extracted by using an end parameter extraction tool such as Star-RCXT. Parasitic parameters can be designed to extract RC parameters, and then they are input into the timing and power consumption analysis tool for timing and power consumption analysis.
8. Post-simulation, timing and power consumption analysis. Post-simulation is also called gate-level simulation, time series simulation and inverse standard simulation. It is necessary to use accurate delay parameters and netlist obtained after local wiring to simulate and verify whether the function and timing of netlist are correct. For example, Primetime-SI can perform timing analysis and signal integrity analysis, crosstalk delay analysis, IR drop analysis and static timing analysis. On the basis of analysis, if there is a clock violation path in the design, Primetime-SI can automatically generate repair files for back-end tools such as Astro. PrimePower has the ability of gate-level power consumption analysis, which can verify the average peak power consumption in the whole IC design, help engineers choose the correct package, determine the heat dissipation and confirm the power consumption of the design. After the design has passed the time sequence and power consumption analysis, PrimeRail carries out static and dynamic voltage drop analysis and electromigration analysis on the design based on technologies such as Star-RCXT, HSPICE, Nanosim and PrimeTime.
9. Revision of 9.ECO (Engineering Change Order). When it is found that there are timing problems or logic errors in individual paths in the final stage of design, it is necessary to modify and reroute the design in a small scope. ECO modification only modifies a small part of the layout without affecting the layout and wiring of the rest of the chip, and the timing information of other parts remains unchanged.
10, physical verification. Physical verification is the design rule check (DRC) of layout and the comparison between logical diagram netlist and layout netlist (LVS). Input the layout into Hercules for layered physical verification to ensure the consistency between the layout and the circuit diagram, which can prevent, find and correct design problems in time. Among them, DRC is used to ensure the manufacturing yield, and LVS is used to confirm whether the netlist structure of the circuit layout is consistent with its original circuit schematic diagram (netlist). LVS can make netlist comparison at device level and function level, and can also compare device parameters, such as MOS circuit channel width/length, capacitance/resistance value, etc.
After completing the above steps, the design can be signed and delivered to the chip factory (slide).