Edit the main features of this paragraph.
1, compatible with MCS5 1 instruction system 2, and the 8k Flash ROM can be erased repeatedly (1000 times or more); 3.32 bidirectional input/output ports; 4.256 x8 internal RAM；; 5. Three 16-bit programmable timers/counters interrupt; 6. The clock frequency is 0-24 MHz; 7, 2 serial interrupts, programmable UART serial channel; 8, 2 external interrupt sources, ***8 interrupt sources; 9.2 Interrupt line in reading and writing, level 3 encryption bit; 10, low-power idle and power-off mode, software setting sleep and wake-up functions; 1 1 has various packaging forms, such as PDIP, PQFP, TQFP and PLCC, to meet the needs of different products.
Edit the pin function and pin voltage of this paragraph.
AT89C52 is an 8-bit general-purpose microprocessor, which adopts the pin diagram of AT89C52 packaged by PDIP industry standard.
Quasi-C5 1 kernel is the same as common 8xc52 in internal function and pin arrangement, and is mainly used for function control during convergence adjustment. The functions include initializing the internal register, data RAM and external interface of the convergence main IC, convergence adjustment control, convergence test chart control, reception and decoding of infrared remote control signal IR, communication with the motherboard CPU, etc. The main pins are XTAL 1( 19 pin) and XTAL2( 18 pin) as the input and output ports of the oscillator, which are externally connected with the 12MHz crystal oscillator. RST/VPD (pin 9) is a reset input port, which is connected to a reset circuit composed of external resistors and capacitors. VCC(40 pins) and VSS(20 pins) are power ports, which are respectively connected to the positive and negative terminals of +5V power supply. P0~P3 are programmable general I/O pins, and their functions and uses are defined by software. In this design, P0 port (pins 32-39) is defined as the function control port of N 1, which is connected with the corresponding function pins of N 1 respectively. Pin 13 is defined as the IR input terminal, pin 10 and pin 65438. Connect the SDAS (pin 1 8) and SCLS (pin 19) ports of n1respectively. /kloc-pin 0/2, pin 27 and pin 28 are defined as handshaking signal function ports, which are connected to the corresponding function terminals of the motherboard CPU, and are used for the detection of the current system and the control function of convergence adjustment state entry.
P0 port
P0 port is a set of 8-bit open-drain bidirectional I/O ports, that is, address/data bus multiplexing ports. When used as an output port, each bit can absorb current to drive eight TTL logic gates, and when writing "1" to port P0, it can be used as a high-resistance input terminal. When accessing external data memory or program memory, this group of port line time-sharing conversion addresses (lower 8 bits) are multiplexed with the data bus, and the internal pull-up resistor is activated when accessing. In Flash programming, P0 port receives instruction bytes, while in program verification, it outputs instruction bytes. External pull-up resistors are required for verification.
P 1 port
P 1 is an 8-bit bidirectional I/O port with built-in pull-up resistor. The output buffer stage of P 1 can drive (sink current or output current) four TTL logic gates. Write "1" to the port, and pull the port high through the internal pull-up resistor. At this time, it can be used as an input port. When it is used as an input port, it will output a current (IIL) when the pin is pulled low by an external signal because there is a pull-up resistor inside. Different from AT89C5 1, P 1.0 and P 1. 1 can also be used as external counting input (P 1.0/T2) and input (P1. During flash programming and program verification, P 1 receives the low-order 8-bit address. Table. Functional characteristics of the second functional pins P 1.0 and P 1. 1
P 1.0 T2, clock output
P 1. 1 T2EX (timer/counter 2)
Port P2
P2 is an 8-bit bidirectional I/O port with built-in pull-up resistor, and the output buffer stage of P2 can drive (sink current or output current) four TTL logic gates. Write "1" to port P2, and pull the port to a high level through an internal pull-up resistor. At this point, it can be used as an input port. When used as an input port, the pin will output current (IIL) when an external signal pulls the pin low due to the internal pull-up resistor. When accessing the external program memory or external data memory with the address of 16 (for example, executing the MOVX @DPTR instruction), P2 port sends out the address data with the upper 8 bits. When accessing an external data memory with an 8-bit address (such as executing MOVX @RI instruction), P2 port outputs the contents of P2 latch. P2 also receives high address and some control signals during flash memory programming or verification.
Port P3
P3 port is a set of 8-bit bidirectional I/O ports with built-in pull-up resistors. P3 output buffer stage can drive (sink or output current) four TTL logic gates. When "1" is written into P3 port, they are pulled high by internal pull-up resistors and can be used as input ports. At this time, P3 port of external pull-down will output current (IIL) through pull-up resistor. Besides being a general I/O port line, P3 port is more important for its second function, that is, it also receives some control signals for flash memory programming and program verification.
Intel's Rapid Storage Technology
Reset input. When the oscillator is working, the RST pin will appear high level for more than two machine cycles, which will reset the single chip microcomputer.
ALE/PROG
When accessing an external program memory or data memory, the ALE (data latch enable) output pulse is used to latch the lower 8-bit word portion of the address. In general, ALE still outputs a fixed pulse signal, and the clock oscillation frequency is 1/6, so it can be used for external clock output and timing purposes. It should be noted that the ALE pulse will be skipped whenever the external data memory is accessed. This pin is also used to input a programming pulse (PROG) during programming the flash memory. If necessary, ALE operation can be prohibited by setting the D0 bit of the 8EH cell in SFR area. When this bit is set, only one MOVX and MOVC command can activate ALE. In addition, when the MCU executes an external program, this pin will be slightly pulled high, and the ALE disable bit should be set to invalid.
PSEN
The output of PSEN is the read strobe signal of external program memory. When AT89C52 fetches instructions (or data) from the external program memory, each machine cycle PSEN is valid twice, that is, two pulses are output. During this period, when accessing the external data memory, the PSEN signal will be skipped twice.
East Asia /VPP
External access rights. In order for CPU to access only external program memory (address 0000H—FFFFH), EA terminal must be kept low (grounded). It should be noted that if the encryption bit LB 1 is programmed, the state of the EA terminal will be internally latched during reset. If the EA terminal is high (connected to the Vcc terminal), the CPU will execute the instructions in the internal program memory. When programming the flash memory, add the programming permission power supply Vpp of+12V to this pin. Of course, this must be the programming voltage Vpp of 12V used by the device.
XTAL 1
Input of oscillator inverting amplifier and internal clock generator.
XTAL2
The output of the oscillator inverting amplifier.
Edit the special function register.
In the AT89C52 on-chip memory, the 80h-FFH * * 128 cell is a special function register (SFE), and the address space mapping of SFR is shown in Table 2. Not all addresses have been defined. Only a part of the bytes from 80h-FFH * * * 128 are defined, and quite a few are undefined. Reading and writing undefined cells will be invalid, the read value will be uncertain, and the written data will be lost. The data "1" should not be written into undefined cells, because these cells may be given new functions in future products. In this case, these single-element values are always "0" after reset. In addition to all timer/counter 0s and timer/counter 1 of AT89C551,AT89C52 has added a timer/counter 2. The control and status bits of timer/counter 2 are located in T2CON (see table 3)T2MOD (see table 4), and the register pairs (RCAO2H, RCAP2L) are the capture/auto-reload registers of timer 2 in 16-bit capture mode or 16-bit auto-overload mode.
Edit this data store.
The internal RAM of AT89C52 is 256 bytes, and the 128 bytes of 80H-FFH overlap the address of SFR, that is, the 128 bytes of RAM are the same as the address of SFR, but they are physically separated. When an instruction accesses an internal address unit above 7FH, the addressing mode used by the instruction is different, that is, the addressing mode determines whether to access a high 128 byte RAM or a special function register. If the instruction is directly addressed, it is accessing a special function register. For example, the following direct addressing instruction accesses the address unit (i.e., P2 port) of the special function register 0A0H. MOV 0A0H, # data indirect addressing instruction accesses high 128 byte RAM. For example, in the following indirect addressing instruction, if the content of R0 is 0AH, the data byte address will be 0AH instead of P2 port (0AH). MOV @R0, # data stack operation is also an indirect addressing mode, so the high-bit 128-bit data RAM can also be used as a stack area. Timer 0 and Timer 1: Timer 0 and Timer 1: AT89C52 work in the same way as AT89C5 1.
Edit this on-chip resource
Timer 2
Basic features: Timer2 is a 16-bit timer/counter. It can be used as both a timer and an external event counter, and its working mode is selected by the C/T2 bit of the special function register T2CON (as shown in Table 3). Timer 2 has three working modes: capture mode, automatic overload (counting up or down) mode and baud rate generator mode, and the working mode is selected by the control bit of T2CON. Timer 2 consists of two 8-bit registers TH2 and TL2. In the timer mode, the value of the TL2 register is increased by 1 every machine cycle. Because a machine cycle consists of 12 oscillation clocks, the counting rate is112 of the oscillation frequency. In the counting mode, when the external input signal on the T2 pin produces a falling edge from 1 to 0, the value of the register increases by 1. In this mode, the external input is sampled during 5SP2 of each machine cycle. If the value obtained in the first machine cycle is 1 and the value obtained in the next machine cycle is 0, the register will be incremented by 1 during S3P 1 in the next cycle. Because it takes 2 machine cycles (24 oscillation cycles) to identify the transition from 1 to 0, the highest counting rate is 1/24 of the oscillation frequency. In order to ensure the correctness of sampling, it is required that the input level should be kept for at least one complete period before changing, so as to ensure that the input signal is sampled at least once. Capture mode: In capture mode, you can select two modes through the T2CON control bit EXEN2. If EXEN2=0, Timer2 is a 16-bit timer or counter. When the overflow is counted, the overflow flag TF2 of T2CON is set and the interrupt is activated. If EXEN2= 1, Timer2 completes the same operation. When the external input signal of T2EX pin transits from 1 to 0 negatively, the values in TH2 and TL2 are also captured in RCAP2H and RCAP2L respectively. In addition, the jump of the T2EX pin signal will set EXF2 in T2CON, which will also activate an interrupt similar to TF2. The capture mode is shown in Figure 4. Automatic overload (counting up or down) mode: Timer2 can be programmed to count up or down when it works in 16-bit automatic overload mode. This function can be selected through the DCEN bit of the special function register T2CON (allowing countdown) (see Table 5). At reset, by default, DCEN is set to "0" and Timer2 is set to count up. When DCEN is set to 1, Timer2 can count up or down, depending on the value of the T2EX pin. As shown in fig. 5, when DCEN=0, Timer2 is automatically set to count up. Thus, the EXEN2 control bit in T2CON has two options. If EXEN2=0, Timer2 counts to 0FFFFH and overflows, and sets TF2 activation interrupt. Reload 16-bit counting registers RCAP2H and RCAP2L at the same time, and the values of RCAP2H and RCAP2L can be preset by software. If EXEN2= 1, the overload of 16 bit of Timer2 is triggered by overflow or the falling edge of external input T2EX from 1 to 0. This pulse sets EXF2, which also generates an interrupt if an interrupt is allowed. The interrupt entry address of timer 2 is: 002BH ——0032H. When DCEN= 1, Timer2 can count up or down, as shown in Figure 6. Thus, the T2EX pin controls the counter direction. When the T2EX pin is logic "1", the timer increments the count. When the count 0FFFFH overflows, TF2 is set, and the 16-bit count registers RCAP2H and RCAP2L are reloaded into TH2 and TL2. When the T2EX pin is logic "0", Timer2 counts down. When the values in TH2 and TL2 are equal to those in RCAP2H and RCAP2L, the count overflows, TF2 is set, and the value of 0FFFFH is reloaded into the timing register. When the timer/counter 2 overflows up or down, the EXF2 position is 1. Baud rate generator: When TCLK and RCLK in T2CON (Table 3) are set, timer/counter 2 is used as baud rate generator. If the timer/counter 2 is used as a transmitter or receiver, the baud rate of its transmission and reception may be different, and the timer 1 is used for other functions, as shown in Figure 7. If RCLK and TCLK are set to 1, timer 2 works in baud rate generator mode. Baud rate generator is similar to automatic overload mode. In this mode, TH2 flip reloads the register of Timer2 with the 16 bit value in RCAP2H and RCAP2L, which is set by software. In mode 1 and mode 3, the baud rate is determined by the overflow rate of timer 2 according to the following formula: baud rate of mode 1 and 3 = overflow rate of timer/16. The timer can work in both timing mode and counting mode, and in most applications, it works in timing mode (C/T2=0). When Timer2 is used as a baud rate generator, its operation is different from that of Timer2. Generally, when used as a timer, the value of the register is increased by 1 (oscillation frequency is112) every machine cycle, while when used as a baud rate generator, the value of the register is increased by 65438+ every state time (oscillation frequency is12). The calculation formula of baud rate is as follows: baud rate of modes 1 and 3 = oscillation frequency /{32*[65536-(RCP2H, RCP2L)]} where (RCP2H, RCP2L) is the unsigned number of 16 bits in RCP2H and RCP2L. The circuit of timer 2 used as baud rate generator is shown in Figure 7. When RCLK or tclk in T2CON =1,the baud rate mode is effective. In baud rate generator working mode, TH2 flip cannot set TF2, so there is no interruption. However, if EXEN2 is set and there is a negative transition from 1 to 0 at T2EX, EXF2 will be set, and the contents of (RCAP2H, RCAP2L) cannot be reloaded into TH2 and TL2. Therefore, when Timer2 is used as a baud rate generator, T2EX can be used as an additional external interrupt source. It should be noted that TH2 and TL2 are inaccessible when Timer2 works at baud rate and as a timer (TR2= 1). Because each state time timer will add 1 at this time, reading and writing it will get an uncertain value. However, for RCAP2, it is readable but not writable, because the write operation will be reloaded, and the write operation may cause write and/or reload errors. Before accessing Timer2 or RCAP2 register, the timer should be turned off (TR2 should be cleared). Programmable clock output: Timer2 can output a clock signal with a duty cycle of 50% from P 1.0 through programming, as shown in Figure 8. The P 1.0 pin is not only a standard I/O port, but also can be used as an external clock input and output clock pulse with 50% duty cycle through programming. When the clock oscillation frequency is 16MHz, the output clock frequency range is 6 1 Hz-4 MHz. When timer/counter 2 is set as a clock generator, C/T2(T2CON. 1)=0, T2OE (T2MOD. 1) = 1, and the timer must be started or stopped by TR2(T2CON.2). The clock output frequency depends on the oscillation frequency and the overloaded value of Timer2 capture registers (RCAP2H, RCAP2L). The formula is as follows: output clock frequency = oscillator frequency /{4*[65536-(RCP2H, RCP2L)]} In clock output mode, the flip of Timer2 will not be interrupted, which is similar to the case when it is used as a baud rate generator. When Timer2 is used as a baud rate generator, it can also be used as a clock generator, but it should be noted that the baud rate and clock output frequency cannot be determined separately because they are the same as RCAP2L and RCAP2L.
UART serial port
The UART working mode of AT89C52 is the same as that of AT89C5 1.
Clock oscillator
AT89C52 has a high gain inverting amplifier, and the pins XTAL 1 and XTAL2 are the input and output terminals of the amplifier respectively. The amplifier forms a self-excited oscillator with an off-chip crystal or ceramic resonator as a feedback element. See figure 10 for the oscillation circuit. The external crystal (or ceramic resonator) and capacitors C 1 and C2 are connected in the feedback loop of the amplifier to form a parallel oscillation circuit. Although there are no strict requirements for external capacitors C 1 and C2, the capacitors will slightly affect the oscillation frequency, oscillator stability, starting difficulty and temperature stability. If the crystal is used, we suggest using 30pF 10pF for the capacitor and 40pF 10pF for the ceramic resonator. Users can also use an external clock. The circuit with external clock is shown in figure 10 on the right. In this case, the external clock pulse is connected to the XTAL 1 terminal, that is, the input terminal of the internal clock generator, and XTAL2 pauses. Because the external clock signal is used as the internal clock signal through the divide-by-two trigger, there is no special requirement for the duty cycle of the external clock signal, but the minimum high-level duration and the maximum low-level duration should meet the requirements of product technical conditions.
Edit this interrupt
AT89C52 *** has six interrupt vectors: two external interrupts (INT0 and INT 1), three timer interrupts (Timer0, 1, 2) and serial interrupt. All these interrupt sources are shown in Figure 9. These interrupt sources can control the permission or prohibition of each interrupt by setting or clearing the special register IE respectively. IE also has a global disable bit EA, which can control whether all interrupts are enabled or disabled. Note that IE.6 in Table 5 is reserved, and IE.5 is also reserved in AT89C5 1. Programmers should not write "1" to these bits. They will be used as extensions of AT89 series products in the future. The interrupt of Timer2 is generated by the logical OR of TF2 and EXF2 in T2CON. When switching to the interrupt service program, these flag bits cannot be cleared by hardware. In fact, the service program needs to determine whether TF2 or EXF2 generates the interrupt, and the software clears the interrupt flag bit. When the timer overflows, the flag bits TF0 and TF 1 of Timer0 and Timer0 are set to the S5P2 state of the machine cycle, and the interrupt flag will not be queried until the next machine cycle. However, in the S2P2 state of the machine cycle where the timer overflows, the flag bit TF2 of Timer2 is set, and the flag is queried in the same machine cycle.
Edit the low power mode in this paragraph.
Idle power saving mode
In idle working mode, the CPU itself is in a sleep state, while all on-chip peripherals remain active, which is generated by software. At this time, the contents of on-chip RAM and all special function registers are frozen at the same time. Any allowed interrupt request or hardware reset can terminate the idle mode. It only takes two machine cycles to terminate the idle state through hardware reset. In this state, the on-chip hardware is prohibited from accessing the internal RAM, but can access the port pin. When the idle mode is terminated by reset, in order to avoid accidental writing to the port, the instruction after activating the idle mode should not be a writing instruction to the port or external memory.
Power failure mode
In power-down mode, the oscillator stops working, and the instruction to enter power-down mode is the last instruction to be executed. The contents of on-chip RAM and special function registers are frozen before the termination of power-down mode. The only way to exit the power-down mode is to reset the hardware. After reset, all special function registers will be redefined, but the contents in RAM will not change. Before Vcc returns to the normal working level, the reset should be invalid, and it must be kept for a certain time before the oscillator can be restarted and work stably.
Edit this segment for programming and encryption.
Flash programming
AT89C52 single chip microcomputer has 8k bytes of Flash memory. This flash memory array has been erased at the factory (that is, the contents of all memory cells are FFH), and users can program it at any time. The programming interface can receive programming permission signals with high voltage (+12V) or low voltage (Vcc). The low-voltage programming mode is suitable for the user's online programming system, and the high-voltage programming mode is compatible with the general EPROM programmer. In AT89C52 MCU, there are some low-voltage programming modes and some high-voltage programming modes. Users can get this information from the model on the chip and reading the signature bytes in the chip. The program memory array of AT89C52 is programmed by byte writing, one byte at a time. In order to write non-empty bytes into the PEROM program memory in the whole chip, the contents of the whole memory must be erased by chip erasure.
programming approach
Before programming, address, data and control signals must be set as shown in Table 9 and Figure 1 1. The programming method of AT89C52 is as follows: 1. Add the address signal of the cell to be programmed to the address line. 2. Add data bytes to be written into the data line. 3. Activate the corresponding control signal. 4. In high voltage programming mode, add+12V programming voltage to EA/Vpp terminal. 5. Write a byte or a program encryption bit for each pair of flash memory arrays, plus an ALE/PROG programming pulse. Each byte write cycle is self-timed, usually about1.5 ms. Repeat step 1-5 to change the address of the programming unit and the written data until all files are programmed.
Encryption of program memory
AT89C52 has three program encryption bits, which can be obtained by programming (P) or not programming (U) the three encryption bits LB 1, LB2 and LB3 on the chip. When the encryption bit LB 1 is programmed, the logic level at the EA terminal is sampled and latched during reset. If the microcontroller is not reset after power-on, the initial value of the latch is a random number, which will remain until the real reset. In order for the microcontroller to work normally, the latched EA level value must be consistent with the current logic level of this pin. In addition, the encrypted bits can only be cleared by the whole erase method.
Query and perspective
AT89C52 MCU uses data pile to indicate the end of a write cycle. In a writing cycle, if the last written byte needs to be read, the highest bit (P0.7) of the read data is opposite to that of the original written byte. After the write cycle is completed, the output data is valid and can be written into the next byte. Data grooming may be effective at any time after the start of the write cycle. Ready/Busy: The progress of byte programming can be monitored by the "RDY/BSY" output signal. During programming, after ALE becomes high level "H", the level of P3.4(RDY/BSY) terminal is pulled down, indicating the programming state (busy state). After the programming is completed, P3.4 becomes high, indicating the ready state. Program verification: If the encryption bits LB 1 and LB2 are not programmed, the code data can be read back to the original data through the address and data line, and the circuit shown in figure 12 is adopted. The encrypted bits cannot be directly verified, and the verification of the encrypted bits can be verified by checking the checksum and write state of the memory. Chip Erase: Using the correct control signal combination (Table 6) and keeping the low-level pulse width of ALE/PROG pin 10mS, the entire PEROM array (4k bytes) and three encrypted bits can be erased. The code array writes any non-empty cells into "1" in the chip erase operation, which needs to be performed before reprogramming. Read the on-chip signature bytes: AT89C52 single chip microcomputer has three signature bytes, the addresses are 030H, 03 1H and 032H respectively. Used to declare the manufacturer, model and programming voltage of the equipment. To read the signature byte of AT89C52, P3.6 and P3.7 should be set to logic low level. The process of reading the signature byte is similar to the normal checking of cells 030H, 03 1H and 032H, except that the meaning of the return value is: (030H)= 1EH, indicating that the product is produced by ATMEL. (03 1H)=52H declared as AT89C52 single chip microcomputer. (032H)=FFH is declared as 12V programming voltage. (032H)=05H declared as 5V programming voltage.