Post CAS: designed to improve the utilization efficiency of DDR II memory. In the post-CAS operation, the CAS signal (read/write/command) may be inserted into the clock cycle after the RAS signal, and the CAS command may remain valid after an extra waiting time. The original tRCD(RAS to CAS and delay) is replaced by al (additive delay), which can be set at 0, 1, 2, 3, 4. Since the CAS signal is one clock cycle later than the RAS signal, the ACT and CAS signals will never conflict.