The running speed of a CPU cannot be judged simply by the main frequency.

Although the main frequency is only 1. The effect of the actual CPU is much higher than that of the previous CPU.

The following information was collected on the Internet.

The lowest frequency of core micro-architecture products is 1.76GHz, and the highest X6800 Extreme Edition is only 2.93GHz, which has been greatly reduced compared with the previous generation Pentium processor with Prescott core. Core 2 processor is divided into two cores, among which the low-end E6300 and E6400 are based on Allendale core, and the other three models, namely E6600, E6700 and X6800, are based on Conroe core. The former has 2MB L2 cache, while the latter has 4MB L2 cache. Other parameters are the same. This time, we tested E6300 based on Allendale core, using 2MB L2.

The design of core microarchitecture mainly has the following improvement features:

14 instruction execution pipeline;

In the past, in order to pursue high frequency, P4 processor based on NetBurst architecture adopted deeper instruction execution pipeline design, such as 20 stages of Williamette and NorthWood, 3 1 stage of Prescott core, and 17 stage of AMD K8 architecture. A longer pipeline will increase the frequency, but the negative effect is that once the branch prediction fails or the buffer hits, more clock cycles will be wasted. Although the improvement of frequency can make up for this defect, the frequency that can be achieved now is obviously not enough to make up for this performance loss. Therefore, the core microarchitecture has designed the 14 instruction execution pipeline, and the shorter pipeline will also make the instruction processing faster. At present, this is a solution that gives consideration to both efficiency and speed.

Wide-area dynamic execution:

Four groups of instruction encoders and three arithmetic logic units: the design of core micro-architecture improves the encoder and arithmetic logic unit to enhance the instruction processing ability. In this respect, a set of innovative functions has been added. Such as wide dynamic execution, macro fusion, micro-operation fusion and so on. Wide dynamic execution and micro-operation fusion are both techniques inherited from the previous generation architecture and then improved and optimized. As for macro fusion, it is the latest addition, which reduces the execution time of instructions by merging ordinary instructions. The above three technologies are the design essence of optimizing the execution efficiency of core micro-architecture instructions.

* * * Enjoy Smart Cache:

In the past, PD series and PXE were independent secondary caches, and the data between cores could only be exchanged through the system bus, which undoubtedly occupied the bus bandwidth and brought delay, which was not conducive to the close cooperation between cores. Conroe has the same * * * secondary cache as Yonah, and uses L2 cache through the internal shared bus router to get rid of the dependence on the system bus. * * * The design of smart cache also balances power consumption and performance well. Under different computing intensities, the core microarchitecture can shut down one core, while the other core uses 4MB L2 cache. When it is not needed, some cache units can be closed to save energy.

Intelligent memory access:

Intelligent memory access includes memory disambiguation and advanced prefetch. Memory disambiguation allows the kernel to intelligently predict the data to be used in memory in advance, thus shortening the waiting time and improving efficiency. After memory disambiguation, the prefetchers set in the L 1 cache and L2 cache will first load the required data into the cache. These two technologies can maximize the use of bus bandwidth and reduce the congestion caused by sudden data exchange.

AMD K8 architecture adds a memory controller, which makes the memory performance of K8 processor stronger. Although Intel has the ability to add a memory controller to the core, for the integrated motherboard and notebook market with huge market share, integrating the memory controller into the Northbridge chip will give better play to the performance of integrated graphics cards and other devices, and it will also be able to follow up the memory upgrade in the future. After adding intelligent memory access technology, the performance gap will be greatly reduced compared with the integrated memory controller.

Advanced digital media enhancements:

Advanced digital media enhancement is an improvement of SSE instruction set in Intel Core microarchitecture, which enables Core microarchitecture to handle 128-bit instructions. Compared with the traditional processor that can only process 64-bit instructions, the core microarchitecture only needs one clock cycle when processing 128-bit instructions, so the performance of processing 128-bit instructions is doubled. When dealing with SSE instruction set data or multimedia operations, advanced digital media enhancement technology will significantly improve efficiency.