If the feedback zero clearing method is used, the state of the input D3D2D 1D0 is arbitrary, regardless of it. Because it is asynchronous clearing, when the clearing signal is enabled, the circuit will be cleared regardless of whether the clock edge comes or not, so the state of 1 1 starting from 0000 should be selected, that is, 10 10. Therefore, the circuit
The output of the NAND gate is connected to the asynchronous clearing terminal (enabled at low level), so that the state of the circuit is 0000-100 10 10, and the circuit will be cleared immediately when it reaches1010, so this state.
Protocol port:
If the IP address is compared to a house, the port is the door of the house. A real house has only a few doors, but an IP address can have as many as 65536 ports (2 16)! Ports are marked with port numbers, which are only integers between 0 and 65535 (2 16- 1).
On the Internet, each host sends and receives data packets through TCP/ip protocol, and each data packet is routed in the Internet according to the ip address of its destination host, and the data packet is successfully transmitted to the destination host.
Most operating systems support multiple programs (processes) running at the same time, so which process should the destination host send the received packets to? Obviously, this problem needs to be solved, so the port mechanism is introduced.