The first stage, design preparation

1. Demand analysis: market research, function comparison with functional chips.

2. Fixed architecture: select appropriate CPU, bus type, various types of IP(RAM, ROM, EEPROM, EFUSE, crystal oscillator, PLL), interfaces (I2C, spi, uart, Jtag, swd),

Protocol, algorithm, watchdog, timer, interrupt, clock reset management, power management, analog circuit (power supply voltage, ADC, charge pump, FET).

3. Write the document: describe the function in general, draw the system architecture and system state jump diagram, describe the functions and registers of each module in detail, and give the functional design diagram and timing diagram.

The second stage is the implementation of the plan.

1. code realization: according to the design scheme specified in the above design preparation stage, the engineer will complete the code realization within the specified time.

In the process of implementation, we should consider: area, speed, clock acquisition, CDC, latch and other design points.

2. Function pre-simulation: Before and during the code implementation, the verification engineer writes verification cases according to each function point in the design scheme, counts the coverage, and ensures the branches and lines in the code.

Toggle, FSM, etc. are covered.

The third stage is time series analysis.

1. Synthesis: After the code implementation and functional simulation are completed, the time sequence constraint file is made according to the design scheme, and the synthesis tool is generated according to the time sequence constraint file.

2. Equivalence check: Using equivalent tools, compare RTL code with comprehensive netlist to check whether they are consistent.

3. Static time series analysis;

Stage 4: Layout and Wiring

1, netlist and library file: after the completion of the third stage, provide the netlist and library file used in the function realization process to the layout house, including:

A. Processing PDK

B. Standard cell library data (lef, lib, cdl, gds)

C. Verification rule files (drc, ant, lvs)

D.QRC technical files, nxtgrd

E. netlist and SDC

Meanwhile, the shape, area and pin coordinates of the block should be provided.

2. Post-function imitation: After providing the above files, layout house will carry out PR to generate netlist with delay information and various corner SDF files. After obtaining the netlist, you need to use the netlist of the function.

Consistency checking, static timing analysis, and checking whether spare doors are added to the netlist.

Then, using this netlist and sdf file, the post-function simulation is carried out (when the test case uses the pre-function simulation). If timing violations are found, the reasons for the violations should be analyzed. according to

The types of reasons for violation can be solved by modifying some codes, ECO, PR maintenance, etc.

If you need to modify the code or ECO, after the modification, you need to repeat the process of the third stage and provide the comprehensive netlist to the layout again. After the layout company returns the netlist and SDF,

Repeat the above inspection and simulation; If PR is fixed, it will be directly modified by layout house. After layout house returns the netlist and SDF, the above-mentioned check and simulation will be repeated.

3. Equivalence check: After you get the netlist, you should go through the formalities, compare the netlist after PR with RTL, and check whether the design is consistent.

4. Timing check: After PR, run post pt again using the netlist, spef file and sdc provided by the layout company. Pay attention to add:

Set propagation clock [all clocks]

Comment out set_ideal_network at the same time. Then analyze the time series report. If it is inconsistent with the results of the time series report provided by PR, find out where the differences are and clean up the time series violations.

Stage 5: Signing

1, review: After the above steps are completed, call relevant designers to review together to ensure that all designs are correct.

A. confirm that all functions are consistent with the design scheme.

B. Confirm that the simulated excitation covers all function points.

C. confirm the GDS, pin connection, power supply and timing relationship of all IPS.

D. Confirm the name, direction and bit width of D2A and A2D ports.

Only when the above items are correctly confirmed can we slide the film.