1, ad 15 ~ ad0: address/data bus
(1)T 1: used as the low 16-bit address a 15 ~ A0.
(2) T2 ~ T4: used as data bus.
2.A 19 ~ A 16/S6 ~ S3: address/status bus.
(1)T 1: The upper 4 bits are used as the address bus, and the memory: the upper 4 bits. I/o: set 0
(2) T2-T4: indicates CPU status information, and S6: continuously low level. S5: When the interrupt permission flag (if in the response flag register) is prefixed. S3, s4: indicates the segment register being used.
20 address lines of 3.8086:
(1) Access to memory: Use 20, address 1M storage space.
(2) Access to I/O port: 64ki/O port can be addressed by 16 A 15 ~ A0.
4.BHE/s7: Bus High Enable/Status s7
(1)t 1: used as bhe, active low.
(2) T2 ~ T4: status signal s7
(3) In 3)dma mode, the pin bit is high impedance state.
Second, the control bus
1, Mn/MX: minimum/maximum mode control line, 32 pins, when connected with +5V: in the minimum mode, 8086 provides all the control signals required by the system, and when grounded: in the maximum mode, the system bus control signal is provided by the dedicated bus controller 8288, and 8086 sends the status signal indicating the current operation (S2 #, s/kloc-
2. Maximum mode. S2×3, s 1×3, s0×3: bus periodic status signal (tri-state, output).
Represents the operation type of 8086 external bus cycle. Rq/gt0/rq/gt 1: request/allow bus access control signal (bidirectional), qs 1, qs0: instruction queue status signal (output), which is used to indicate the status of instruction queue in 8086 internal BIU. Lock: bus priority lock signal (output, tri-state). When the lock output is low, the external processor cannot.
3. Minimum mode. M/IO: Memory /IO control signal (output, three states).
When m/iox = h: memory, when m/iox = l: I/o port. DT/R: data sending/receiving signal (output, tri-state), when DT/R× X = H: writing, when DT/R× 3 = L: reading, data allowing signal (output, tri-state) is valid during the period after CPU accesses memory or I/O bus, and is used as a bus transceiver in the system.
4. Hold: Hold the request signal (input). When the external logic sets the hold pin to a high power level, the 8086 enters the hold state after completing the current bus cycle and gives up the bus control right. HLDA: Hold response signal (output), which is the response signal of CPU to Hold signal, and the output is low. When the HLDA signal is valid, the tri-state signal lines of 8086 are all in tri-state (high resistance), which makes.
5.ALE: address lock enable signal (output), T 1 sends out a positive pulse, latches the address information on the bus into the address latch on the falling edge, and interrupts the response signal (output, three states). When the 8086 responds to the maskable interrupt request from the intr pin, inta goes low during the interrupt response, wr: write control signal (output, tri-state).
6. The control line (bus) is not affected by Mn/MX. Rd: Read control signal (output, three states). When the power supply voltage is low, the CPU is reading data. Ready: Wait for the state control signal, also called the ready signal (input). Ready = h: CPU waiting, ready = l: peripheral ready, INTR: interrupt request signal (input). A high level indicates an interrupt request.
7. Test control signal (input), CPU test, high level continues to wait, low level leaves to wait, reset: reset signal (input), advanced system resets internal flag register fr, segment register, instruction pointer ip and instruction queue to initial state. Note: the initialization state of code segment cs is ffffh.
8. Other signals CLK: clock signal (input) VCC: power supply, ++5V 10%% grounding: ground wire. Common signal pins of two ground wires: ad 15 ~ ad0: address/data ad 19 ~ ad 16/S6 ~ S3: address data/status bhe×/S7: high allowable (output) Mn/MX×: maximum and minimum (output) m/io.
9. output den: data enable (output) hold: hold request signal (input) hlda: hold response signal (output) ale: address lock enable signal (output) inta: interrupt response signal (output) rd: read control signal (output) wr: write control signal (output) ready: wait state control signal (input) intr: interrupt.
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