The module designer describes his design in the same way as programming through the language of hardware design. If some modules are available (such as those bought by other companies or inherited from previous designs), just use them directly.
Every design engineer must have at least two or three verification engineers, who just help to see if there are any bugs in the design.
After each module is designed, put all the designs together and then verify the error correction. If there is nothing wrong, it is being thrown to the circuit engineer to study the arrangement of cables and the like.
1, design definition and synthesis RTL code. The design definition describes the overall structure, specification parameters, module division, used interfaces, etc. Then the designer designs the modules according to the functional modules divided by the hardware design or reuses the existing IP cores. Usually, the hardware description language is used to describe the behavior of the circuit at the register transfer level, and Verilog/VHDL is used to describe the connection between logic units and the connection between input/output ports and logic units. The gate-level netlist describes the circuit with logical units, forms the circuit with instantiation and defines the hierarchical structure of the circuit.
Pre-simulation, also known as RTL level simulation or functional simulation. Whether the logic function of the circuit is effective is verified by HDL simulator. In pre-simulation, it is usually irrelevant to the specific circuit implementation, and there is no timing information.
2. Logical synthesis. Establish a design and synthesis environment, input RTL source code into a synthesis tool, such as DesignCompiler, add constraints to the design, and then logically synthesize the design to obtain a gate-level netlist that meets the design requirements. The gate netlist can be stored in ddc format. The logic synthesis of circuits generally consists of three steps: transformation, logic optimization and mapping. Firstly, the RTL source code is converted into a general Boolean equation (GTECH format). The process of logic optimization attempts to complete the combination of library cells, so that the combined circuit can best meet the requirements of design function, timing and area; Finally, the logic units of the target process library are mapped into a gate-level netlist, which requires the process technology library of the semiconductor manufacturer to get the delay of each logic unit when mapping the circuit diagram. The results after synthesis include the timing and area of the circuit.
3. Layout planning. After getting the gate-level netlist, input the results into JupiterXT for layout planning. Layout planning includes macro-cell layout, power network synthesis and analysis, communication analysis, layout optimization and time sequence analysis.
4. Unit layout and optimization. Cell layout and optimization mainly define the placement position of each standard cell and optimize it according to the placement position. EDA tools widely support physical synthesis, unify layout and optimization with logical synthesis, introduce real connection information, and reduce the number of iterations required for time series convergence. Input the designed layout and gate-level netlist into a physical synthesis tool, such as PhysicalCompiler, for physical synthesis and optimization. In PC, the design can be optimized in terms of timing, power consumption, area and routability to achieve the best result quality.
5. Static timing analysis (STA), formal verification (FV) and testability circuit insertion (DFT).
Static time series analysis is a detailed analysis method. By analyzing the delay information of all paths in the extraction circuit, the delay of the signal on the time sequence path is calculated, and the errors that violate the time sequence constraints such as whether the setup time and the hold time meet the requirements are found out.