Comparison with traditional embedded interconnection methods
Figure 1 shows the application of RapidIO interconnection in embedded system. With the continuous development of high-performance embedded systems, the interconnection between chips and boards requires higher and higher bandwidth, cost, flexibility and reliability. Traditional interconnection methods, such as processor bus, PCI bus and Ethernet, can hardly meet the new requirements.
Table 1 summarizes and compares three interconnection technologies with bandwidth up to loGb/S: Ethernet, PCIEXpress and serial RapidIO. It can be seen that serial RapidIO is most suitable for high-performance embedded system applications.
Serial RapidIO protocol
RapidIO Industry Association was established in 2000, and its purpose is to develop reliable, high-performance and packet-based embedded systems. Interconnection technology based on. Serial RapidIO is a RapidIO standard, and the physical layer adopts serial differential analog signal transmission. RapidIO 1。 X standard supports signal rates of 1.25GHZ, 2.5GHZ and 3. 125GHz; ; The RapidIO2.0 standard under development will support 5GHZ and 6.25GHZ.
At present, almost all suppliers of embedded system chips and equipment have joined the RapidIO Industry Association. Take Texas Instruments as an example. TI joined the organization on 200 1 and became a member of the leading committee in 2003. At the end of 2005, TI launched the first DSP integrated with SRIO, and then launched the * * * 5 DSPs supporting SRIO, which enabled the application of RapidIO to be fully developed.
RapidIO-only protocol structure and packet format
In order to meet the requirements of flexibility and scalability, RapidIO protocol is divided into three layers: logical layer, transport layer and physical layer, as shown in Figure 2. The logical layer defines the operation protocol; The transport layer defines packet switching, routing and addressing mechanisms; The physical layer defines electrical characteristics, link control and error correction retransmission.
Like Ethernet, RapidIO is an interconnection technology based on packet switching. As shown in Figure 3, the RapidIO packet consists of a header, optional payload data and a 16 CRC check. Due to different packet types, the length of the packet header can be ten to twenty bytes. The length of payload data in each packet is less than 256 bytes, which is beneficial to reduce transmission delay and simplify hardware implementation.
The above definition of packet format takes into account the efficiency of packet and the simplicity of packet assembly/unpacking. RapidIO switching equipment only needs to analyze the front and back 16 bits and the source/destination device ID, which simplifies the implementation of switching equipment.
Logical layer protocol
The logical layer defines the operation protocol and the corresponding packet format. The logical layer services supported by RapidIO are mainly direct IO/DMA (direct IO/ direct memory access) and message passing.
Direct IO/DMA mode is the simplest and most practical transmission mode, provided that the master device knows the memory mapping of the accessed end. In this mode, the master device can directly read and write the memory of the slave device, while the direct IO/DMA function of the accessed device is often completely realized by hardware, so the accessed device will not have any software burden. Functionally, this function is similar to the traditional host interface (HPI) of TI DSP. However, compared with HPI port, SRIO has larger bandwidth, fewer pins and more flexible transmission mode.
The message passing mode is similar to the Ethernet transmission mode, and the master device does not need to know the memory state of the accessed device. The location of data in the accessed device is determined by the mailbox number (similar to the end slogan in Ethernet protocol). The slave device saves the data into the corresponding cache according to the mailbox number of the received data packet. This process is often not completely realized by hardware, but needs software assistance, so it will bring some software burden.
Transport layer protocol
RapidIO is an interconnection technology based on packet switching, and the transport layer defines the routing and addressing mechanism of packet switching.
RapidIO network is mainly composed of an endpoint and a switch. Terminal devices are the source or destination of data packets, and different terminal devices are distinguished by device ID. RapidIO supports 8-bit or 16-bit device ID, so the RapidIO network can accommodate up to 256 or 65536 terminal devices. Similar to Ethernet, RapidIO also supports broadcast or multicast, and each terminal device can be configured with a broadcast or multicast ID in addition to its unique device ID. The switching device forwards the packet according to the destination device ID of the packet, but the switching device itself has no device ID.
RapidIO's interconnection topology is very flexible. Besides switching devices, two terminal devices can also be directly interconnected. Take the TMS320C6455DSP of TI as an example. It has four SRIO ports of 125G, and the supported topology is shown in Figure 4.
Physical layer protocol
RapidIO 1。 X protocol defines the following two physical layer interface standards: 8/ 16 parallel LVDS protocol and 1X/4x serial protocol (SRIO).
Parallel RapidIO is difficult to be widely used because there are many signal lines (40 ~ 76), while 1X/4x serial RapidIO has only four or 16 signal lines, which has gradually become the mainstream.
Based on SerDes technology, serial RapidIO has been widely used in backplane interconnection. It uses differential AC coupled signals. Differential AC coupled signal has the advantages of strong anti-interference, high speed and long transmission distance. The quality of differential AC coupled signal is not measured by traditional time series parameters, but by eye diagram. The wider the "eye" in the eye diagram, the better the signal quality. Fig. 5 is a typical serial RapidIO signal eye diagram.
In order to support full-duplex transmission, serial RapidIO receives and sends signals independently, so each serial RapidIO port consists of four signal lines. The standard lx/4x serial RapidIO interface supports 4 ports and *** 16 signal lines. These four ports can be used as independent interfaces to transmit different data; It can also be combined as an interface to improve the throughput of a single interface.
The standard 1x/4x serial RapidIO interface is integrated on the MS320C6455 DSP of TI, as shown in Figure 6.
When sending, the logic layer and the transport layer encode the assembled data packet by CRC and send it to the FIFO of the physical layer. The 8b/ 10b encoding module encodes every 8 bits of data into 10 bits, and the parallel/serial conversion module converts 10 bits of parallel data into serial bits. The sending module converts digital bits into differential AC coupled signals and sends them out on the signal line. The process of receiving? On the contrary.
Application of serial RapidIO in wireless infrastructure
Wireless infrastructure such as base stations and media gateways are typical high-performance embedded communication systems, and they all have very high requirements on the bandwidth, delay, complexity, flexibility and reliability of interconnection. Serial RapidIO is the best choice to meet these requirements.
Take the wireless base station as an example. Before SRIO appeared, the typical block diagram of baseband processing of wireless base station is shown in Figure 7.
In traditional base stations, the interconnection between DSP and ASIC or FPGA is generally based on external memory interface (EMIF), and the interconnection between DSP or DSP and host is generally based on HPI or PCI. Their main disadvantages are: small bandwidth, many signal lines, master-slave interface, and no support for point-to-point transmission. In addition, DSP can not directly carry out backplane transmission.
Using SRIO can effectively solve these problems and greatly improve the interconnection performance of wireless base stations. Fig. 8 shows a block diagram of baseband interconnection of wireless base stations. Here, SRIO realizes the interconnection between most devices, and even supports DSP direct backplane transmission.
The flexibility of baseband processing can be further improved by the interconnection of SRIO switching devices. Fig. 9 shows a block diagram of a baseband SRIO switching interconnect. This interconnection is conducive to the realization of advanced baseband processing resource pool architecture, and data can be sent to any processor interconnected by SRIO switch, thus realizing the load balance of each processor and making more effective use of the overall processing capacity of the system.
To sum up, serial RapidIO is the best interconnection technology for embedded systems, especially wireless infrastructure. Bandwidth up to 10Gb/s, low latency and low software complexity meet the stringent performance requirements of the rapidly developing communication technology. The serial differential analog signal technology meets the limitation of the system on the number of pins and the demand of backplane transmission; Flexible point-to-point peer-to-peer interconnection, exchange interconnection, optional1.25g/2.5g/3.125g, can meet the needs of many different applications.